The present invention relates to multistack 3-dimensional semiconductor structures. In addition, the present invention relates to a method for fabricating the multistack 3-dimensional semiconductor structures. According to the present invention, active devices are formed on a semiconductor substrate followed by adhering a second semiconductor layer above the active devices and then building active devices on this additional semiconductor layer. The present invention makes it possible to obtain improvements in function, density and performance as compared to multistack devices previously suggested.
Planar technology is principally used currently for fabricating semiconductor surfaces. The level of integration that can be achieved on a semiconductor chip is limited by the size of the chip and by the structural fineness that is obtainable. The performance of a system which is realized using planar technology and which comprises a plurality of chips connected to one another is restricted by the number of possible connections between individual chips via connection contacts, the signal transmission speed that can be achieved via such connections (the so-called frequency performance) and also by the power consumption.
In order to overcome these restrictions, three-dimensional circuit arrangements have been suggested. In such arrangement, a plurality of chip planes are arranged one above the other in the third-dimensional circuit arrangements. The necessary electrical connections between the chip planes are produced by making direct contact.
For example, it has been suggested for producing three-dimensional integrated circuits, to deposit a further semiconductor layer on a substrate in which a plane of components has been produced. The semiconductor layer is recrystallized for instance by laser annealing. A further component plane is then realized in the recrystallized layer. The components produced in the substrate prior to the deposition of the further semiconductor are exposed during the recrystallization step to the thermal loading associated with the laser annealing, which leads to a very limited yield for the chips due to large numbers of defects which typically occur.
It has also been suggested to produce a three-dimensional integrated circuit by first producing the individual component planes separately from one another in different substrates. The substrates are then thinned to a few microns in thickness and are connected to one another with the aid of the wafer bonding method. For the electrical connection of the various component planes, the thin substrates are provided on their front and rear sides with contacts for subsequent interchip connections. This has the disadvantage that the thinned wafers have to be processed on both the front and rear sides. However, rear side processes are not provided in the standard planar technology. A number of handling problems remain unsolved in connection with this method. A further disadvantage of this particular method is that the functionality of the individual component planes cannot easily be tested before they are joined together, since individual components, but not completed circuits, are produced in each individual plane.
In addition, there have been suggestions for fabricating three-dimensional devices by creating the desired devices on individual semiconductor wafers prior to bonding them together to form the multilevel device. However, a major problem associated with this approach is that very precise alignment is required between the chips since the chips have already been built and are complete prior to the bonding. It is not entirely apparent how this precision alignment can be achieved on a practical basis. Furthermore, these processes require substantial thinning of one of the wafers by grinding or etching on the back side such as from a thickness of about 10-20 mils down to about 5 microns. This is an extremely different procedure to carry out. Moreover, great difficulties exist in controlling the thickness uniformity.
Accordingly, it would be desirable to provide three-dimensional multilayer devices that did not require the precise alignment as mentioned above.
The present invention provides for a multistack three-dimensional semiconductor structure that does not require the precision alignment of prior art devices. Moreover, the multistack three-dimensional semiconductor structures of the present invention make possible improvements in function, density and performance of the devices.
More particularly, the present invention relates to a multistack three-dimensional semiconductor structure that comprises a first level structure comprising a semiconductor substrate and first active devices. A second level structure comprising a SOI semiconductor structure is bonded to the first level structure and further comprises second active devices. The first active devices according to the present invention are more heat tolerant in device design than the second active devices.
In addition, the present invention relates to a method for fabricating a multistack three-dimensional semiconductor structure. The method comprises providing a first level structure comprising a semiconductor substrate and first active devices. A layer of insulation is provided on the first level structure and electrical interconnections are provided to connect selected portions of the first level structure to subsequently to be provided second level structure.
A second semiconductor structure is bonded on top of the insulating layer. The thickness of the semiconductor structure is reduced followed by forming second active devices on the semiconductor structure. The first active devices are more heat tolerant in device design than the second active devices. Electrical connections are created between the first level structure and second active devices.
The present invention also relates to semiconductor devices obtained by the above-described process.
Still other objects and advantages of the present invention will become readily apparent by those skilled in the art from the following detailed description, wherein it is shown and described preferred embodiments of the invention, simply by way of illustration of the best mode contemplated of carrying out the invention. As will be realized the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, without departing from the invention. Accordingly, the description is to be regarded as illustrative in nature and not as restrictive.